There is continuing demand for semiconductor devices that have higher speed, lower power consumption, and higher integration density. The integration density can be increased by minimizing the dimensions of various elements, such as the width of gate lines, the junction depth of source/drain regions, and the sectional area of contacts. However, such microscopic patterns may increase the resistance of the semiconductor device, slow the operating speed, and/or increase the power consumption of the semiconductor device.
One method of solving the above-stated problems is to use metal silicide, which is a compound of a metal and silicon, in place of polysilicon. Examples of metal silicides include tungsten silicon, titanium silicide, and cobalt silicide. Because cobalt silicide is generally thermally and chemically stable and has a small sheet resistance, it is widely used for semiconductor devices that require high speed operation, low power consumption, and/or high integration density. When forming a cobalt silicide layer, a cobalt layer and a barrier metal layer may be sequentially stacked on a silicon surface and subjected to primary annealing, stripping to remove the unreacted cobalt layer and the barrier metal layer, and secondary annealing.
Conventionally, when forming a cobalt salicide layer, a cobalt layer that is formed by physical vapor Deposition (PVD) (PVD cobalt layer) may be used. (hereinafter a cobalt salicide layer formed using a PVD cobalt layer is referred to as a “PVD cobalt salicide layer.”) Because it may include slight impurities and may prevent the formation of an interfacial oxide layer, the PVD cobalt salicide layer has a relatively low sheet resistance. Moreover, the PVD cobalt salicide layer is generally stable to a subsequent thermal budget, resulting in a relatively small junction leakage current. Therefore, the PVD cobalt salicide layer is commonly used in high-speed semiconductor memory devices.
However, the microscopic fine patterns resulting from increased integration density may raise problems when forming the salicide layer by a conventional method. For example, as the gate width decreased to less than 90 nm, the PVD cobalt salicide layer formed on a gate line may become agglomerated in subsequent annealing. When agglomeration occurs, the sheet resistance of the PVD cobalt salicide layer may increase, which may obstruct high speed operation. Furthermore, more severe agglomeration may cause disconnection of the PVD cobalt salicide layer.
One method suggested to solve the agglomeration problem is to form a Ni salicide layer or a NiTa salicide layer on the gate line instead of a PVD cobalt salicide layer. Even when formed on a gate line narrower than 90 nm, however, the Ni salicide layer or NiTa salicide layer suffer virtually no agglomeration in subsequent annealing. However, the NiSi layer phase shifts into a NiSi2 layer during the subsequent annealing, which increases its sheet resistance. Accordingly, to use the Ni salicide layer or the NiTa salicide layer, the subsequent annealing must be changed, which may require reinvestment in manufacturing facilities and/or other costs. As a result, it may be expensive and time consuming to form the Ni salicide layer or the NiTa salicide layer.
When the salicide layer is formed on source/drain regions, it is desirable to prevent increases in junction leakage in spite of forming microscopic patterns.
Particularly, a cobalt salicide layer formed using a cobalt layer deposited by CVD (hereinafter referred to as a “CVD cobalt salicide layer”) involves generally severe topography on its bottom surface profile and relatively high junction leakage current.
U.S. Pat. No. 6,514,859 to Erhardt et al., entitled “Method of Salicide Formation with a Double Gate Silicide,” discloses one way of decreasing the resistance of a gate line and improving the characteristic of junction leakage current in the source/drain junction area. According to this patent, silicidation is performed twice to make the silicide layer thick on the upper surface of the gate line. On the other hand, silicidation is performed once to make the silicide layer thin on the source/drain junction area. This is achieved by extra patterning to expose the gate line after forming a barrier insulating layer such as an SOG layer. Consequently, the manufacturing process may be complicated and expensive.